module check_onehot
#(
    parameter DW = 8
)
(
    input   [DW-1:0]    in,
    output              out
);

wire [DW-1:0]   in_xor;
wire [DW-1:0]   in_inv;

assign in_xor[0]=in[0];
generate
    genvar v;
    for(v=1; v<DW; v=v+1)begin
        assign in_xor[v] = in[v]^in_xor[v-1];
    end
endgenerate

assign in_inv = ~in;

assign out = (&(in_inv|in_xor)) & (|in_inv);

endmodule


module check_onehot1
#(
    parameter   DW  = 8 
)
(
    input   [DW-1:0]    in,
    output              out
);

wire [DW-1:0] onehot_list;

generate
    genvar v;
    for(v=0; v<DW; v=v+1)begin
        assign onehot_list = (in == {{(DW-1-v){1'b0}}, 1'b1, {v{1'b0}}}) ? 1'b1 : 1'b0;
    end
endgenerate

assign out = |onehot_list;

endmodule